This project is considered as a complementary tool for publishing
the results of reversible logic (definitions)
synthesis. In the very limited space of any standard publication,
only the cost calculation is usually shown, whereas the actual designs
would be of more interest. Some authors use non-standard gates, others
use their own metric for the calculation of the circuit cost, which further
complicates comparison of the circuit designs. Here, an approach for a unified comparison of the
results is suggested, where any author can
publish their design and/or compare it with already posted ones.
In order to unify the different gate libraries and cost metrics the following
restrictions apply. First, the synthesis is done with common (in this
area) restrictions: no
fan-outs and no feedbacks. Second, the synthesis is preferred to be
done
in one of the following libraries:
NCT:
NOT, CNOT, Toffoli. This gate library was introduced by Toffoli in
his 1980 paper. This library is the smallest complete set of gates.
However,
an additional garbage bit (not every reversible specification can be
realized
with zero garbage) may be required by this model.
NCTSF:
NOT, CNOT, Toffoli, SWAP, Fredkin. This library adds SWAP and
original Fredkin gate to the previous library. Fredkin gates are of
interest as in some technologies they have a small cost. Inclusions:
NCTSF>NCT.
GT:
generalized (n-bit) Toffoli. This gate library is complete
and does not require additional garbage for any reversible
specification.
However, some of the gates in this library are expected to have a high
technological cost. Inclusions: GT>NCT.
GT&GF:
generalized Toffoli and generalized (n-bit) Fredkin. The
largest gate library. Inclusions: GT&GF>GT, GT&GF>NCTSF,
GT&GF>NCT.
Input constants are preset to either 0 or 1 by the designer. Finally,
the resulting cost is measured with three numbers: garbage, number of
gates and quantum cost . All results
are published in two formats: machine-readable
format and a picture with optional author comments. Everyone is
welcome to submit their results in the
machine-readable format for the immediate publication on this website
as long as no better design is already published.
Circuits for the following benchmark
functions are currently available: