COMPUTER SCIENCE 350
COMPUTER ARCHITECTURE
SPRING TERM 2002
http://www.csc.uvic.ca/~csc350/
CHECK your csc.uvic.ca email regularly. I will provide interesting and important notices (eg exam dates) to you by email.
AND Check the course web page - http://www.csc.uvic.ca/~csc350/
This prospectus, copies of all of the visual aids
used in class, assignments and interesting URLS are all there.
Lectures:
M, Tu, Wed CLE A 201, 1530-1630
Office Hours: 1100 - 1130 every day
Instructor
Eric Manning
Engineering Office Wing, rm. 329
Email: emanning@csr.uvic.ca (answered daily)
The Instructor:
Eric Manning is Nortel Networks / New Media Centre Professor of Computer Science and of Electrical and Computer Engineering at UVic, Director of the Parallel, Networked and Distributed Computing & Applications Group (PANDA), and former Dean of Engineering (UVic) . His interest in computer architecture goes back to 1965, when he wrote a PhD thesis on hardware architecture design principles to aid fault tolerance. Since then he has followed developments in architecture, and has occasionally contributed original work, because of its bearing on his research in computer networks and in distributed systems. Plus, he thinks it's an interesting subject!
He is a Fellow of the IEEE and of the Engineering
Institute of Canada, President of the Canadian Association for Computer
Science / Association informatique canadienne, and is listed in Who’s
Who in America, Who’s Who in the West and Who’s Who in Canada.. He
has consuilted widely for industry and government in Canada, the United
Startes and Japan. He is an Honorary Professor of South East University,
Nanjing, PRC. He is currently working on the design of internets to carry
multimedia traffic with guaranteed Quality of Service.
Teaching Assistant: James CALVER jcalver@csr.csc.UVic.CA
Office Hours: 2-3 pm Mon Wed, ELW A224. Assignments to be put in the Csc350 Assignment Drop
box.
Prerequisites: C Sc 225, C Sc 230, and C Sc 250 / 355, or written permission of the department.
Recommended Prerequisite/Corequisite: CS 360,
Operating Systems. CS 350 is much easier if you have taken or are taking
CS 360.
Textbooks & Supplies
"Computer Organization and Design: The Hardware/Software Interface ", second edition.
David A. Patterson University of California, Berkeley and John L. Hennessy Stanford University
Morgan Kaufman Publishers. ISBN 1-55860 - 281 - X
"CS 350 Visual Aids", visual aids used in lectures and available at
http://www.csc.uvic.ca/~csc350/VISAIDS.HTML
I cover these far too quickly to permit
hand-copying them in lecture. The thing to do is to print them out
beforehand and bring them to class. There’s plenty of white space on the
images and you can make notes right on your paper copies.
Course Objectives
The course will introduce the architectural techniques used to design and build modern high-performance microprocessors and microcomputers. Today's humblest microprocessors use advanced architectural techniques which were found in only the most exotic supercomputers of a decade ago; we will study and evaluate these sophisticated techniques. This knowledge is valuable if you want to 1] design a microprocessor (unlikely), 2] configure a microprocessor-based system (more likely) , 3] write code or a compiler for a microprocessor which takes advantage of the advanced architectural techniques (more likely) or simply 4] choose a microprocessor (very likely).
Topics
The course covers instruction set processor architecture, basic processor implementation techniques including microprogramming, pipelining, memory hierarchy design, storage systems, interconnects. Representative architectures, especially RISC architecture, will be discussed. Time permitting, we will discuss multiprocessors and parallel machines at the end of course.
Course Grading
Assignments 25%
Midterm Exam (mid - Feb.) 25%
Final Examination 40%
Class participation 10%
All assignments are due at the Teaching Assistant's designated dropoff point by 1700 hours on the date specified ("due date").
All written material, including assignments and exams, must be your own work. Plagiarism and Cheating: Assignment solutions and exam answers must be entirely your own work. My policy towards plagiarism is zero tolerance, for reasons I will explain in class. Evidence of plagiarism will result in a course grade of 0 (zero) for all parties implicated.
Late assignments will be graded by
GA = G / 2n where
GA is the grade awarded
G is the grade according to the marking scheme
n is the number of days late.
For example, the grade will be divided by 4 if the assignment is turned in 2 days late.
Class participation:
You earn your class participation marks as follows:
1]
*Obtain a head-and-shoulders picture of yourself (a passport photo, a snapshot or a photo
from the machines they have in K-Marts will be fine).
*Affix it to a sheet of 8.5 by 11 inch paper, 3-hole punched.
*Print your name and ID on the upper right corner of the page, surname first.
*Give it to me during the first two weeks of classes.
This will allow me to associate your face with your name.
If you omit to to do this I cannot offer you class participation marks.
2] Participate in class discussions. Ask questions. Offer observations
You are responsible for all of the
visual aids and all of the sections/Chapters of the text listed
as "Patterson-Hennesey Breaks or Phbreaks, below.
All exams will be open book
(When’s the last time an employer asked you to solve a problem without
reference materials?) and you will have to have a copy of the text and
copies of the visual aids to write them successfully.
Topic ref to visaids Textref
________________________________________________________________
1. Introduction PT1.pdf
.1 Computer as levels
hardware & software interchangeable
migration to hardware
.2 process concept & definition
.3 PHbreak: PH Chapters 1 & 2
__________________________
2. Level 1: Gross Organization
(Review)
.1 computer = cpu + busses + I/O PT2.1.pdf
cpu = control + ALU + registers
busses = Mp bus + I/O bus
cpu as interpreter
interrupts
PHbreak_interrupts PHSec 5.6
**next assgt 2.6.8
.2 Flynn classification: SISD, MISD, PT2.2.pdf
SIMD, MIMD
Pipelining cpu
PHbreak_ PH Ch6 (lookahead)
Pipelining logic net
.3 Primary Memory Mp PT2.3.pdf
functional definition & current numbers
gate realization
tagged
PHbreak_history_ PHSec 7.7
associative
.4 Secondary Memory Ms PT2.4.pdf
tape, disc
floppy disc
Winchester
PHbreak_I/Odevices_ PHSec8.3
drum 2.27
optical store
CCD & bubble
Mass Stores
.5 I/O : a hardware/software tradeoff PT2.5.pdf
copyloop
DMA/Block Transfer Controller
PHbreak_DMA PHSec 8.5
channels
PHbreak_I/O PHSec 8.4-8.6
IOProcessor
.6 Busses, interconnects &datacomm PT2.6.pdf
PHbreak_Busses PH sec8.4
unibus
crossbar
ring
Banyan
block&character-synced I/O
PHbreak_ review_Chapter 8
________________
3. Level 2
the Conventional Machine Level: ISP
.1 classical AC,MQ PT3.1.pdf
single-address architecture
PHbreak: MIPS ISP - Ch 3 (readahead)
.2
CISC: System 360/370/390 PT3.2.pdf
360 ISP
.3 DEC PDP-11 ISP PT3.3.pdf
.4 PHbreak: DEC VAX ISP PT3.4.pdf
(PDP-11 extension) Appendix
End of Part 1
PART II
.5 PHbreak¬es: RISC architecture PT3.5.pdf
& the MIPS cpu
.6 CDC 6600 supercomputer
ISP & architecture PT3.6.pdf
4. microsteps : the SimpleMachine PT4.1.PDF
5. MIPS Control - wired logic
6. Pipelining: the MIPS cpu PT6.PDF
as a case study
.1 PHbreak PH Ch 6
____________
Level 3
the Operating System
Machine Level:
7. From Program relocation to virtual memory PT7.PDF
.1 relocation register
.2 base & bound -single segment
.3 multiple segments & segment box
.4 plus pages
.5 capabilities
PHBreak: MIPS chip VM: PH Ch 7.4
.7 **addslides** PHBreak:
8. storage hierarchy & caches PT8.PDF
________________
9. Level 1
Microprogramming Level PT9.PDF
4. sequential machine models
4. control types discussed: {sync, wired},
{sync, mprogrammed}, {async, wired}
.1 control functionality,
microstep = f(order, tau)
.2 computing order and tau in hardware
.3 SimpleMachine & instr definition
sequences & timing diagrams
.4 (part of) wired sync control
for SimpleMachine
.5 synchronous microprogrammed control;
horizontal variety
.6 synchronous microprogrammed control;
vertical variety
.7 RISC blows it all away -
back to hardwired sync control
.8 Implementing the MIPS ISP in
wired logic: PH Sec 5.1- 5.4
.9 PHbreak: Implementing the MIPS ISP in microprogramming, Sec 5.5, PT9.9.PDF
Appendix
________________
10. Level 1
Asynchronism PT10.PDF XX
.1 Async wired control
.2 bus asynchronism -remember the Unibus
________________
11. Future Trends:
.1 RISC - passing fad? PT11.1.PDF XXX
The CISC comeback?
.2 Multiprocessors & parallel machines PT11.2.PDF XXX
.3 the end of microelectronic progress? PT11.3.PDF XX
.4 no more clocks - asynchronous design PT11.4.PDF XX
Grade Conversion:
Numerical scores may be adjusted to achieve a satisfactory distributioin of grades, owing to the difficulty of predicting just how easy or difficult students may find a given examination.
Numerical scores will be converted to letter grades as follows:
Over-all Course % Grade Assigned Letter Grade
90 - 100 A+
85 - 89 A
80 - 84 A-
75 - 79 B+
70 - 74 B
65 - 69 B-
60 - 64 C+
55 - 59 C
50 - 54 D
< 50 F
The dividing lines between letter grades may be lowered by up to 3% to account for natural breaks in the numeric scores. Note that there will be no retests and no E grades in this course.
You must pass the final exam in order to pass the
course.
GUIDELINES CONCERNING FRAUD
These guidelines concern the type of fraud where a student presents another's work as his or her own, or allows another to do so.
1. As fraud invalidates the evaluation of a student's progress, it is the duty of instructors, teaching assistants, and laboratory assistants to take measures to prevent fraud and to be vigilant towards symptoms of fraud.
2. Students are encouraged to study together. But, unless the contrary is indicated, submitted work is to be done by students individually.
The sharing of program code electronically or by other means is forbidden unless specifically approved in advance by the course instructor.
Students are to collaborate on submitted work only when this is explicitly permitted by the instructor. In such a case, the names of all students who have collaborated on a piece of submitted work should be indicated on all submitted material.
As in all academic endeavour, due credit must be given to all reference material. Students should consult the course instructor if they are not certain which outside material is appropriate for use in a course.
The collaboration is to involve reasonable effort on the part of all students involved. In a situation where this is clearly not the case, appropriate action will be taken with regard to those students who have not fully contributed to the collaborative effort.
3. In case fraud is detected, credit is withheld
from the work affected. The students involved are reported to the Department
Chair who may take additional disciplinary action commensurate with the
severity of the fraud and the past records of the students. Actions that
may be taken include: no marks for the piece of work; failure in the course;
or, in repeat cases, withdrawal from the program or the University.