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Journal and Conference
90
E. Kontopidi & J. C. Muzio, The Partitioning of
Linear Registers for Testing Applications, Microelectronics
Journal, Vol. 24, pp. 533 - 546, 1993.
89
C. Feng, J.C. Muzio & F. Lombardi, On the Testability of Array
Structures for FFT Computation,
J. of Electronic Testing, Theory and Applications,
Vol. 4, pp. 215 - 224, 1993.
88
X. Luo & J. C. Muzio, Checkers for the 1-out of-3 Code and the
2-out of-3 Code, Proc. 1993 Canadian
Conf. on Very Large Scale Integration, pp. 5B-7 -
5B-12, 1993.
87
D. Wessels & J.C. Muzio,
Probabilistic Identification of Critical
Components for Circuit Delays,
Proc. 1993 IEEE International Workshop on Defect and
Fault Tolerance in VLSI Systems, pp. 215 - 222,
1993.
86
X. Luo & J. C. Muzio, A Novel Cache Memory for Multiprocessor
Systems, Proc. of IEEE Pac.
Rim Conf. on Comm., Comp., & Sign. Proc., pp.
145 - 148, 1993 (abstract refereed).
85
P.K. Lui & J.C. Muzio,
Boolean Matrix Transforms for the
Minimization of Modulo-2 Canonical Expansions, IEEE Trans. on
Computers, Vol. 41, pp. 342 - 348, 1992.
84
F. Lombardi, Y.N. Shen & J.C. Muzio, An FFT Architecture for WSI
with Concurrent Error Detection
and Fault Location, IEE Proc., Part E,
Vol. 139, pp. 13 - 20, 1992.
83
P.K. Lui & J.C. Muzio, Structure
of Modulo-2 Ring Sum Canonical Expansions for Boolean Functions,
International J. of
Electronics, Vol. 72, pp. 21 - 35, 1992.
82
D. Wessels & J.C. Muzio,
PLA Decomposition to Reduce the Cost of
Concurrent Checking, Proc.
1992 IEEE Int. Wkshp. on Defect & Fault Tolerance in
VLSI Sys., pp. 117 - 126, 1992.
81
E. Kontopidi & J.C. Muzio, The Partitioning of Linear
Registers for Testing Applications, Proc.
1992 Can. Conf. on Very Large Scale
Integration, pp. 292 - 300, 1992.
80
D. Wessels & J. C. Muzio,
Concurrent Checking and Unidirectional
Errors in Multiple-Valued
Circuits, Proc. of 22nd Int. Symp. on Mult.
Val. Logic, pp. 292 - 299, 1992, (IEEE Conf).
79
J.C. Muzio & M. Serra, Data
Compaction for Bridging Faults, Computer Systems, Science and
Engineering, Vol. 6, pp. 131 - 142,
1991.
78
P.K. Lui & J.C. Muzio, Constrained Parity Testing, J. of
Electronic Testing, Theory and Applications,
Vol. 2, pp. 279 - 291, 1991.
77
S. Zhang, D.M. Miller & J. C. Muzio, The Determination of Minimal
Cost One-Dimensional Linear
Hybrid Cellular Automata, Elec. Lett.,Vol. 27,
pp. 1625 - 1627, 1991.
76
P.K. Lui & J.C. Muzio,
Boolean Matrix Transforms for the Parity
Spectrum and Minimization of
Modulo-2 Canonical Expansions, IEE Proc., Part
E, Vol. 138, pp. 411 - 417, 1991.
75
D.M. Miller, J. C. Muzio, M. Serra, X. Sun, S. Zhang & R.
D. McLeod,
Cellular Automata Techniques
for Compaction Based BIST, Proc. IEEE
Int. Symp. on Circs. & Sys., 1991.
74
F. Lombardi & J.C. Muzio, Concurrent Error Detection and Fault
Location in Reconfigurable
Structures for FFT Computation, Proc. IEEE
Int. Conf. on Wafer Scale Integration, pp. 47 - 53,
San
Francisco, 1991.
73
M. Serra, T.Slater, J.C. Muzio and D.M.Miller, The Analysis of
Linear Cellular Automata and their Aliasing Properties, IEEE
Trans. Computer-Aided Design of Int. Circs. and Sys., Vol. 9, pp.
767 - 778,
1990.
72
D. Wessels & J.C. Muzio, Concurrent Checking of PLA Primary
Inputs and Applications in
Multiple-Component Circuits, J. Semi-Custom
ICs, Vol. 8, pp. 16 - 28, 1990.
71
P.K. Lui & J.C. Muzio, Simplified Theory of Boolean Functions,
International J. of Electronics,
Vol. 68, pp. 329 - 341, 1990.
70
F. Lombardi, Y.N. Shen & J.C. Muzio, On the Testability of Array
Structures for FFT Computation,
Proc. 2nd IEEE Int. Symp. on Parallel and Dist.
Processing, pp. 519 - 522, 1990.
69
J.C. Muzio, Concerning the Maximum Size of Terms in the
Realization of Symmetric Functions,
Proc. of 20th Int. Symp. on Multiple Valued Logic,
pp. 292 - 299, 1990, (IEEE Conference).
68
P.K. Lui & J.C. Muzio, The Testing of Feedback Bridging Faults
between the Outputs and Inputs of a
Combinational Network, Computer Systems,
Science and Engineering, Vol. 4, pp. 12 - 18, 1989.
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