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Books
1
J.C. Muzio & T.C. Wesselkamper, Multiple-Valued
Switching Theory, Adam Hilger, Boston, 1986.
2
S.L. Hurst, D.M. Miller and J. C. Muzio, Spectral
Techniques in Digital Logic, New York and London:
Academic Press, 1985, 314 pp.
Journal and Conference
146
J. Rice & J. C. Muzio,
Properties of Autocorrelation
Coefficients, 2003 IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing,
145
J. Zhong & J. C. Muzio, A Comparison of Generators for
Testing Sequential Circuits Using BIST, International Workshop
on Logic Synthesis, Laguna Beach, 2003.
144
J. Rice & J. C. Muzio,On the Use of Autocorrelation
Coefficients in the Identification of Three Level decompositions,
International Workshop on Logic Synthesis, Laguna Beach, 2003,.
143
L. T. Yang & J.C. Muzio,
A High Level Data Path
Allocation Algorithm Based on BIST Testability Metrics, Proc.
14th IEEE International Conference on Microelectronics, 2002.
142
L. T. Yang & J.C. Muzio, An Improved BIST Testability
Metric Based High Level Test Synthesis Approach, Proc. 2002
International Conference on VLSI, pp. 78 - 85, 2002.
141
L. T. Yang & J.C. Muzio,
Introducing Redundant Transformations
for Built-in Self-Testable Data Path Allocation, Proc. 2002 IEEE
International Conference on Communications, Circuits and Systems,
Vol. 2, pp. 1346 - 1350, 2002.
140
J. Rice & J. C. Muzio,
Use of the Autocorrelation
Function in the Classification of Switching Functions, Proc.
Euromicro Symposium on Digital System Design, pp. 244 251, 2002.
139
J. Rice & J. C. Muzio,
Antisymmetries in the Realization
of Boolean Functions, IEEE International Symposium on Circuits
and Systems, CD ROM Paper 2666, 2002.
138
L. T. Yang & J.C. Muzio, Introducing Redundant
Transformations for High Level Built-in Self-Testable Synthesis,
Proc. 9th International Conference on Electronics,
Circuits and Systems, Vol. 2, pp. 475 - 479, 2002.
137
L. T. Yang & J.C. Muzio, Redundant Transformations for
the Testability Metric Based Built-in Self-Testable Data Path
Allocation, Proc. 2002 IEEE Asia-Pacific Conference on Circuits
and Systems, pp. 28 - 31, 2002.
136
L. T. Yang & J.C. Muzio, Redundant Transformations for
the Testability Metric Based High Level Built-in Self-Testable
Synthesis Proc. XVII International Conference on Design of
Circuits and Integrated Systems, 2002.
135
M. Serra & J.C. Muzio,
The IT Support for Acquired Brain
Injury Patients the Design and
Evaluation of a New Software Package,
Hawaii
International Conference on System Sciences - 35, 2002.
134
L. T. Yang & J.C. Muzio,
An Improved High-Level Built-In
Self-Test Synthesis Algorithm, Proc.
8th IEEE International Conference on Electronic
Circuits and Systems, Vol. 1, pp. 549 552, 2001.
133
L. T. Yang & J.C. Muzio, An Improved Register Transfer Level
Built-In Self-Test Partitioning,
Proc. 9th International Symposium on
Integrated Circuits, Devices and Systems, pp. 414 417, 2001.
.
132
L. T. Yang & J.C. Muzio, High-Level Test Synthesis for
Built-In Self-Testable Designs, Proc. XIV Symposium on
Integrated Circuits and System Design, pp. 115 121, 2001.
131
L. T. Yang & J.C. Muzio, A BIST Testability Metric-Based
Algorithm to Integrate Scheduling and Allocation in High Level Test
Synthesis, Proc. 9th International Symposium on
Integrated Circuits,
Devices and Systems, pp. 409 413, 2001.
130
J.C. Muzio & M. Serra,
HCI Challenges in Designing for Users with
Disabilities, Proc. 9th
International Conference on Human-Computer
Interaction, Vol. 1, pp. 46 50, 2001.
129
J. Bingham & J.C. Muzio,
Advanced Evolution of Nonlinear
Cellular Automata for Combinational
BIST, European Test Workshop, 2001.
128
K. Kent, J.C. Muzio & G. Shoja, Remote Transparent Execution of
Java Threads, Proc. 2001 High Performance Computing Symposium,
pp. 184 191, 2001.
127
L. T. Yang & J.C. Muzio,
A Register-Transfer Level BIST
Partitioning Approach for ASIC Designs,
Proc. 2001 IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing,
pp. 275 278, 2001.
126
L. T. Yang & J.C. Muzio,
High-Level Data Path Synthesis for Built-In Self-Test Designs,
Proc. 2001
IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing, pp. 279 282,
2001.
125
L. T. Yang & J.C. Muzio,
Built-In Self-Testable Data Path
Synthesis, Proc. 2001 IEEE Computer
Society Annual Workshop on VLSI (WVLSI 2001), pp. 78
84, 2001.
124
E. V. Dubrova & J. C. Muzio,
Easily Testable
Multiple-Valued Logic Circuits Derived from
Reed-Muller Circuits, IEEE Trans. Computers,
Vol. 49, pp. 1285 - 1289, 2000.
123
E. Bonneville, J.C. Muzio & M. Serra,
Usability Issues in
Software to Assist People with Brain
Injuries, Proc. 6th ERCIM Workshop
on User Interfaces for All, pp. 42 56, 2000.
122
J. Rice & J. C. Muzio,
Two New Methods for Calculating
Autocorrelation Coefficients, Proc. 4th International Workshop
on Boolean Problems, pp. 69 - 76, 2000.
121
M. Serra, E. Wang & J. C. Muzio,
Using Multimedia in a
Digital Design Lab, Proc. , European
Workshop on Microelectronics Education, 2000.
Appearing in Microelectronics Education
(ed. B.Courtois, N.Guillemot, G.Kamarinos &
G.Stιhelin), pp. 139 142, Kluwer Academic Publishers,
2000.
120 E. Dubrova, P. Ellervee, D.M. Miller & J. C. Muzio,
TOP:
An Algorithm for Three-Level Optimization
of PLDs, Proc. Design,
Automation and Test in Europe Conference, pp. 751, 2000.
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